The present invention relates generally to circuit characterization, and more particularly relates to techniques for characterizing an impact on delay induced by the switching history of a circuit.
In circuits fabricated using a partially depleted silicon-on-insulator (SOI) process, circuit delay is typically a function of the switching history of the circuits. For example, a complementary metal-oxide-semiconductor (CMOS) SOI circuit when switched after remaining idle for a relatively long period of time (e.g., a few milliseconds), referred to as a first switch (1SW), will typically have a longer or shorter delay than if the circuit switches again, referred to as a second switch (2SW), within a relatively short period of time (e.g., a few nanoseconds). This effect, often referred to as SOI history, can be a critical factor in determining the worst and best case performance of an SOI circuit. SOI history is generally determined as a tradeoff among the effects of drain-to-body and source-to-body leakage currents (long time constants) and very rapid dynamic capacitive coupling effects in a device. The presence of gate-to-body tunneling can be an additional factor.
Conventionally, experiments performed to evaluate SOI history effects are primarily delay chain experiments, in which steady state delays are measured and compared with delays for different input patterns. The measurement of SOI history generally involves input pulse widths on the order of a few nanoseconds (ns) and a picosecond (ps) time resolution. Such history measurements, however, have not agreed particularly well with model predictions. Furthermore, the history measurements, and delay measurements obtained therefrom, are typically performed on limited hardware using costly high-speed probing techniques and equipment, and require significant test time. These measurements, however, are difficult to obtain during processing in a manufacturing environment due, at least in part, to such problems as, for example, noise, shielding, test time, etc.
Experiments have shown that the SOI history may be as high as thirty percent in present CMOS technology, and such SOI history is significantly dependent on device design. Moreover, SOI history variation across a wafer may be in excess of five percent, and the effects of intrinsic parameter variations on SOI history is not well understood due, in part, to a limited amount of data collected.
There exists a need, therefore, for a methodology for accurately measuring SOI history that does not suffer from the problems present in conventional testing methods, some of which were described above.
The present invention provides techniques for accurately characterizing the change in delay induced by the switching history, which may be defined as a difference between the first switch delay and the second switch delay, of a circuit or device.
In accordance with one embodiment of the invention, apparatus for characterizing an impact on delay induced by the switching history of a circuit includes a pulse generator configurable for generating a signal having a pulse width that is selectively adjustable, the signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another. The apparatus also includes a first delay circuit coupled to the pulse generator, the first delay circuit being configurable for receiving the signal from the pulse generator and generating a version of the signal at an output of the first delay circuit, the first delay circuit having a first switch delay characteristic of the first edge of the received signal and a second switch delay characteristic of the second edge of the received signal, wherein the pulse width of the signal generated by the pulse generator is less than the first switch delay associated with the first delay circuit.
The apparatus further includes a controller, operative to: (i) vary the pulse width of the signal generated by the pulse generator; (ii) monitor the version of the signal at the output of the first delay circuit; (iii) determine a value of the pulse width that defines a boundary of when the version of the signal is present at the output of the first delay circuit and when the version of the signal is not present; and (iv) determine a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby the impact on delay induced by the switching history of the circuit to be characterized is a function of the ratio.
In accordance with another embodiment of the invention, a method for characterizing a change in delay induced by a switching history of a circuit includes the steps of: generating a signal having a pulse width that is selectively adjustable, the signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another; generating a delayed version of the signal, the delayed version of the signal having a first switch delay characteristic of the first edge of the signal and a second switch delay characteristic of the second edge of the signal, wherein the pulse width of the signal is less than the first switch delay associated with the delayed version of the signal; varying the pulse width of the signal; monitoring the delayed version of the signal; determining a value of the pulse width that defines a boundary of when the delayed version of the signal is present and when the delayed version of the signal is not present; and determining a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby the change in delay induced by the switching history of the circuit to be characterized is a function of the ratio.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.